Digital VLSI Architectures for Advanced Channel Decoders

Error-correcting codes are strongly adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probes. New and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. This work aims to focus on Polar codes, which are a recent class of channel codes with the proven ability to reduce decoding error probability arbitrarily small as the block-length is increased, provided that the code rate is less than the capacity of the channel. This property and the recursive code-construction of this algorithms attracted wide interest from the communications community. Hardware architectures with reduced complexity can efficiently implement a polar codes decoder using either successive cancellation approximation or belief propagation algorithms. The latter offers higher throughput at high signal-to-noise ratio thanks to the inherently parallel decision-making capability of such decoder type. A new analysis on belief propagation scheduling algorithms for polar codes and on interconnection structure of the decoding trellis not covered in literature is also presented. It allowed to achieve an hardware implementation that increase the maximum information throughput under belief propagation decoding while also minimizing the implementation complexity

An LDPC Decoder Architecture for Wireless Sensor Network Applications

The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce the dissipated energy per transmitted bit with respect to uncoded communication. Different Low Density Parity Check (LDPC) codes are considered to this purpose and post layout results are shown for a low-area low-energy decoder, which offers percentage energy savings with respect to the uncoded solution in the range of 40%–80%, depending on considered environment, distance and bit error rate

Unruptured Aneurysms Italian Study (UAIS) background and method

Treatment of unruptured cerebral aneurysms still represents an unsettled question in neurosurgical and neuroradiological communities. Although nowadays the indication for treatment have become relatively clear, indeed uncertainity remains for what concerns the proper treatment modality (surgical or endovascular) in terms of both the risk and the mid and long-term efficacy of the two procedures. The "Unruptured Aneurysms Italian Study" is a cooperative prospective study which aims to delineate the "State of the Art" in a nation based population. It has been designed: 1) to depict the nationwide modality of treatment of Unruptured Aneurysms, 2) to assess in the most objective way the overall treatment-related mortality and morbidity as well as the surgical and endovascular risk in the respective patient populations (it is not a surgical versus endovascular study) and 3) to asses the efficacy of the different procedures in the mid and long term periods. The study started on June 2003 and to June 2006, 637 patients have been enrolled. The study will end when the 1000th patient is enrolled